module SAD_3BY3 (DATA_L, DATA_R, DATA_O);

	input 	[71:0] DATA_L, DATA_R;
	output 	[7:0]	DATA_O;
	wire 	D00,D10,D20,
			D30,D40,D50,
			D60,D70,D80;
			
assign DATA_O =D00+D10+D20+D30+D40+D50+D60+D70+D80;

AD_1BY1 U0	(.iLDATA(DATA_L[7:0]),
			.iRDATA(DATA_R[7:0]),
			.AD(D00));
AD_1BY1 U1	(.iLDATA(DATA_L[15:8]),
			.iRDATA(DATA_R[15:8]),
			.AD(D10));
AD_1BY1 U2	(.iLDATA(DATA_L[23:16]),
			.iRDATA(DATA_R[23:16]),
			.AD(D20));
AD_1BY1 U3	(.iLDATA(DATA_L[31:24]),
			.iRDATA(DATA_R[31:24]),
			.AD(D30));
AD_1BY1 U4	(.iLDATA(DATA_L[39:32]),
			.iRDATA(DATA_R[39:32]),
			.AD(D40));
AD_1BY1 U5	(.iLDATA(DATA_L[47:40]),
			.iRDATA(DATA_R[47:40]),
			.AD(D50));
AD_1BY1 U6	(.iLDATA(DATA_L[55:48]),
			.iRDATA(DATA_R[55:48]),
			.AD(D60));
AD_1BY1 U7	(.iLDATA(DATA_L[63:56]),
			.iRDATA(DATA_R[63:56]),
			.AD(D70));
AD_1BY1 U8	(.iLDATA(DATA_L[71:64]),
			.iRDATA(DATA_R[71:64]),
			.AD(D80));						
endmodule	